Radio frequency (RF) laterally diffused metal-oxide semiconductor (LDMOS) power transistors provide good performance in the frequency range that are used in cellular base stations, and like applications. Typically, a high power LDMOS uses wires and on-chip integrated capacitors to achieve an impedance match for device input and output. The device includes a chip with input and output wires that extend over at least part of the chip to capacitors at outboard sides of the device, and a ground shield to minimize or prevent interference resulting from electromagnetic fields generated when current flows through the wires. The use of a so-called Faraday Shield to reduce interference is well known, but shield designs vary.
U.S. Pat. No. 6,744,117 relates to a method of manufacturing RF LDMOS and shows a ground shield that has two metal layers. Briefly, FIGS. 2 and 3 of the '117 patent shows a first ground shield formed (by metallic deposit), along with a first set of drain contacts. A second interlevel dielectric layer (ILD1) is formed over the first ground shield and the contacts. The second ohmic or metal layer is then formed over ILD1 and is patterned to provide a ground shield and drain contacts. The second ground shield has electrical connection with first ground shield. The structure shown is suitable for plastic packaging.
Another LDMOS ground shield design is shown in FIG. 1, in top view. This design shows a shielded device 10 that includes a chip 24 with an output ground shield 18 and input ground shield 19. The device 10 has circuitry 26, inboard wire pads 12, 13 on either side of the circuitry 26, each having an outboard wire pad 14, 15, respectively, for wire connection on over the ground shield on each side of the device. The capacitors 16, formed on chip 24, are located along the opposed sides of the device. Wires, not shown, extend over a portion of the chip 24 from inboard pad 12 to outboard pad 14; and from inboard pad 13 to outboard pad 15. Thus, the wires cross over above the ground shields 18, 19 and these shields must prevent or minimize interference from and loss by the overhead wires. The ground shields 18, 19 are each continuous, stretching along the entire length of the device where there are overhead wires, to shield it. The shields 18, 19 are each of two metal layers, with the upper layer and lower layer (not shown). An array of vias 20 extends beneath the upper metal layer and represents the only discontinuities in the topography of upper metal layer.
With a large, high-powered device, heat is generated during operation, and metallic components tend to expand at a higher rate, and to a greater extent, with increase in temperature than semiconductor materials because of differences in coefficients of thermal expansion (CTE). This expansion differential introduces mechanical stresses into the device that might shorten its life, or affect performance, or both. Because of these CTE differences, the ground shield as described in FIG. 1 is susceptible to thermally-induced stress (metal has a higher coefficient of thermal expansion than the chip) leading to passivation cracks and delamination. Further, there is an adverse etch loading effect during fabrication of the shield at the contacts and vias due to the large areas to be etched.
Accordingly, it is desirable to develop ground shields, especially for large, high-powered LDMOS, which are more compatible with the coefficient of thermal expansion of the semiconductor materials of the device, while at the same time providing good shielding from electromagnetic effects. It is further desirable to reduce the etch loading effect at contact and via during fabrication of these shields. In addition it is also desirable that the shields are suitable for manufacture with automated design tools. These and other desirable features and characteristics of the embodiments of the present disclosure will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.